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?2000 integrated device technology, inc.
dsc-3490/6 1 high-speed clock-to-data output times ? military: 20/25ns (max.) ? commercial: 12/15/20ns (max.) low-power operation ? idt70914s active: 850 mw (typ.) standby: 50 mw (typ.) architecture based on dual-port ram cells ? allows full simultaneous access from both ports synchronous operation ? 4ns setup to clock, 1ns hold on all control, data, and address inputs ? data input, address, and control registers ? fast 12ns clock to data out ? self-timed write allows fast cycle times ? 16ns cycle times, 60mhz operation ttl-compatible, single 5v ( + 10%) power supply clock enable feature guaranteed data output hold times available in 68-pin plcc, and 80-pin tqfp military product compliant to mil-prf-38535 qml industrial temperature range (-40c to +85c) is available for selected speeds. recommended for replacement of idt7099 (4k x 9) if separate 9th bit data control signals are not required. high speed 36k (4k x 9) synchronous dual-port ram idt70914s memor y array i/o 0-8l oe l clk l clken l r/ w l ce l self- timed write logic reg reg en reg en register register memory array write logic sense amps write logic sense amps decoder decoder self- timed write logic reg i/o 0-8r oe r clk r clken r r/ w r ce r 3490 drw 01 a 0l -a 11l a 0r -a 11r
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 2 , 3490 drw 03 10 11 12 13 14 15 16 50 49 48 47 46 45 44 index 17 18 19 20 21 22 23 24 25 26 51 52 53 54 55 56 57 58 59 60 98765432 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 a 6l a 7l a 8l a 9l a 10l a 11l oe l v cc r/ w l n/c n/c ce l gnd i/o 8l i/o 7l i/o 6l n / c i / o 5 l v c c i / o 4 l i / o 3 l i / o 2 l i / o 1 l i / o 0 l g n d g n d i / o 0 r i / o 1 r i / o 2 r i / o 3 r v c c i / o 4 r i / o 5 r a 7r a 8r a 9r a 10r a 11r oe r gnd gnd r/ w r n/c n/c ce r gnd i/o 8r i/o 7r i/o 6r a 5 l a 4 l a 3 l a 2 l a 1 l a 0 l c l k e n l c l k l c l k r c l k e n r a 0 r a 1 r a 2 r a 3 r a 4 r a 5 r a 6 r idt70914j j68-1 (4) 68-pin plcc top view (5) n/c n/c
!" # the idt70914 is a high-speed 4k x 9 bit synchronous dual-port ram. the memory array is based on dual-port memory cells to allow simultaneous access from both ports. registers on control, data, and address inputs provide low set-up and hold times. the timing latitude provided by this approach allow systems to be designed with very short cycle times. with an input data register, this device has been optimized for applications having unidirectional data flow or bi-directional data flow in bursts. the idt70914 utilizes a 9-bit wide data path to allow for parity at the user's option. this feature is especially useful in data communication applications where it is necessary to use a parity bit for transmission/ reception error checking. fabricated using idt?s cmos high-performance technology, these dual-ports typically operate on only 850mw of power at maximum high- speed clock-to-data output times as fast as 12ns. an automatic power down feature, controlled by ce , permits the on-chip circuitry of each port to enter a very low standby power mode. the idt70914 is packaged in a 68-pin plcc, and an 80-pin tqfp. military grade product is manufactured in compliance with the latest revision of mil-prf-38535 qml, making it ideally suited for military temperature applications demanding the highest level of performance and reliability. notes: 1. all v cc pins must be connected to power supply. 2. all ground pins must be connected to ground supply. 3. j68-1 package body is approximately .95 in x .95 in x .17 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 3 notes: 1. all v cc pins must be connected to power supply. 2. all ground pins must be connected to ground supply. 3. pn80-1 package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
!" $%" reference n/c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 3490 drw 04 idt70914pf pn80-1 (4) 80-pin tqfp top view (5) n/c a 6l a 7l a 8l a 9l a 10l a 11l n/c oe l v cc r/ w l n/c ce l gnd i/o 8l i/o 7l i/o 6l n/c a 7r a 8r a 9r a 10r a 1 1r n/c oe r gnd gnd r/ w r n/c ce r gnd i/o 8r i/o 7r i/o 6r n/c c l k e n l c l k e n r n/c n/c n/c n/c n / c n / c i / o 5 l v c c i / o 4 l i / o 3 l i / o 2 l i / o 1 l i / o 0 l g n d g n d i / o 0 r i / o 1 r i / o 2 r i / o 3 r v c c i / o 4 r i / o 5 r n / c n / c n / c n / c a 5 l a 4 l a 3 l a 2 l a 1 l a 0 l c l k l c l k r a 0 r a 1 r a 2 r a 3 r a 4 r a 5 r a 6 r n / c ,
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 4 & ' ()'(# *# +,##-. . /0% .1
2" ++(# + notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v cc + 10%. 34 5
" 4 5(# *# +,##-.
" notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. # * /607 /
% 48 9 " *:(- notes: 1. this is the parameter t a . this is the "instant on" casae temperature. 2. industrial temperature: for specific speeds, packages and powers contact your notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed v cc + 10%. note: 1. at v cc < 2.0v, input leakages are undefined symbol rating commercial & industrial military unit v te rm (2) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v v te rm (2) terminal voltage -0.5 to v cc -0.5 to v cc v t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -65 to +150 -65 to +150 o c i out dc output current 50 50 ma 3490 tbl 01 grade ambient temperature gnd v cc military -55 o c to+125 o c0v 5.0v + 10% commercial 0 o c to +70 o c0v 5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 3490 tbl 02 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2) v v il input low voltage -0.5 (1) ____ 0.8 v 3490 tbl 03 symbol parameter conditions max. unit c in input capacitance v in = 3dv 8 pf c out outp ut capacitance v out = 3dv 9 pf 3490 tbl 04 symbol parameter test conditions 70914s unit min. max. |i li | input leakage current (1) v cc = 5.5v, v in = 0v to v cc ___ 10 a |i lo | output leakage current ce = v ih , v out = 0v to v cc ___ 10 a v ol output low voltage i ol = +4ma ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ v 3490 tbl 05
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 5 & ' ()'(# *# +,##-. ; 0" . /0.1
2" notes: 1. at f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. vcc = 5v, t a = 25 c for typ, and are not production tested. i cc dc = 150ma (typ). 5. industrial temperature: for specific speeds, packages and powers contact your sales office. 70914s12 com'l only 70914s15 com'l only symbol parameter test condition version typ. (2 ) max. typ. (2 ) max. unit i cc dynamic operating current (bo th ports active ) ce l and ce r = v il , outputs disabled f = f max (1 ) com'l 190 310 180 300 ma mil & ind ____ ____ ____ ____ i sb1 standby current (bo th po rts - ttl le v e l inp uts ) ce l and ce r = v ih f = f max (1 ) com'l 95 150 90 140 ma mil & ind ____ ____ ____ ____ i sb2 standby current (one po rt - ttl le v e l inp uts ) ce "a " = v il and ce "b " = v ih (3 ) a c tiv e p o rt o utp uts disabled, f=f max (1 ) com'l 170 220 160 210 ma mil & ind ____ ____ ____ ____ i sb3 full standby curre nt (bo th p o rts - all cm os le v e l inp uts ) both ports ce r and ce l > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (2 ) com'l 10151015 ma mil & ind ____ ____ ____ ____ i sb4 full standby curre nt (one po rt - all cmos le v e l inp uts ) ce "a " < 0.2v and ce "b " > v cc - 0.2v (3 ) v in > v cc - 0.2v or v in < 0.2v, active port outputs disabled f = f max (1 ) com'l 165 210 155 200 ma mil & ind ____ ____ ____ ____ 3490 tb l 06a 70914s20 com'l & military 70914s25 military only symbol parameter test condition version typ. (2 ) max. typ. (2 ) max. unit i cc dynamic operating current (bo th ports active ) ce l and ce r = v il , outputs disabled f = f max (1 ) com'l 170 290 ____ ____ ma mil & ind 170 310 160 290 i sb1 standby current (bo th po rts - ttl le v e l inp uts ) ce l and ce r = v ih f = f max (1 ) com'l 85 130 ____ ____ ma mil & ind 85 140 80 130 i sb2 standby current (one po rt - ttl le v e l inp uts ) ce "a " = v il and ce "b " = v ih (3 ) a c tiv e p o rt o utp uts disabled, f=f max (1 ) com'l 150 200 ____ ____ ma mil & ind 150 210 140 200 i sb3 full standby curre nt (bo th p o rts - all cm os le v e l inp uts ) both ports ce r and ce l > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (2 ) com'l 10 15 ____ ____ ma mil & ind 10 20 10 20 i sb4 full standby curre nt (one po rt - all cmos le v e l inp uts ) ce "a " < 0.2v and ce "b " > v cc - 0.2v (3 ) v in > v cc - 0.2v or v in < 0.2v, active port outputs disabled f = f max (1 ) com'l 145 190 ____ ____ ma mil & ind 145 200 135 190 3490 tb l 06b
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 6 figure 3. typical output derating (lumped capacitive load). figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. *+ input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1,2 and 3 3490 tbl 07 3490 drw 06 893 ? 30pf 347 ? 5v data out 893 ? 5pf* 347 ? 5v data out 3490 drw 05 1 2 3 4 5 6 7 8 20 40 100 60 80 120 140 160 180 200 ? tcd (typical, ns) capacitance (pf) 3490 drw 07 <
- 9pf is the i/o capacitance of this device, and 30pf is the ac test load capacitance ,
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 7 & ' ()'(# *# + +=-*" !" >. /0.1
2 * / 76? 7@4 ->. /0.1
2 * /<0076
07" notes: 1. transition is measured 0mv from low or high impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. industrial temperature: for specific speeds, packages and powers contact your sales office. 70914s12 com'l only 70914s15 com'l only symbol parameter min. max. min. max. unit t cy c clock cycle time 16 ____ 20 ____ ns t ch clock high time 6 ____ 6 ____ ns t cl clock low time 6 ____ 6 ____ ns t cd clock high to output valid ____ 12 ____ 15 ns t s registered signal set-up time 4 ____ 4 ____ ns t h registered signal hold time 1 ____ 1 ____ ns t dc data output hold after clo ck hig h 3 ____ 3 ____ ns t cklz clock high to output low-z (1,2) 2 ____ 2 ____ ns t ckhz clock high to output high-z (1,2) ____ 7 ____ 7ns t oe output enable to output valid ____ 7 ____ 8ns t ol z output enable to output low-z (1,2) 0 ____ 0 ____ ns t ohz output disab le to outp ut high-z (1,2) ____ 7 ____ 7ns t sck clock enable, disable set-up time 4 ____ 4 ____ ns t hck clock enable, disable hold time 2 ____ 2 ____ ns port-to-port delay t cwdd write port clock hig h to read data delay ____ 25 ____ 30 ns t cs s clock-to-clock setup time ____ 13 ____ 15 ns 3490 tbl 08a 70914s20 com'l & military 70914s25 military only symbol parameter min. max. min. max. unit t cy c clock cycle time 20 ____ 25 ____ ns t ch clock high time 8 ____ 10 ____ ns t cl clock low time 8 ____ 10 ____ ns t cd clock high to output valid ____ 20 ____ 25 ns t s registered signal set-up time 5 ____ 6 ____ ns t h registered signal hold time 1 ____ 1 ____ ns t dc data o utp ut ho ld a fte r clo c k hig h 3 ____ 3 ____ ns t cklz clock high to output low-z (1,2) 2 ____ 2 ____ ns t ckhz clock high to output high-z (1,2) ____ 9 ____ 12 ns t oe output enable to output valid ____ 10 ____ 12 ns t ol z output enable to output low-z (1,2) 0 ____ 0 ____ ns t ohz o utp ut dis ab le to outp ut hig h-z (1,2) ____ 9 ____ 11 ns t sck clock enable, disable set-up time 5 ____ 6 ____ ns t hck clock enable, disable hold time 2 ____ 2 ____ ns port-to-port delay t cwdd write port clock hig h to read data delay ____ 35 ____ 45 ns t cs s clock-to-clock setup time ____ 15 ____ 20 ns 3490 tbl 08b
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 8 *= ) +- &',+ notes: 1. transition is measured 200mv from low or high-impedance voltage with the output test load (figure 2). 2. ce l = ce r = v il , clken l = clken r = v il. 3. oe = v il for the reading port, port 'b'. 4. all timing is the same for left and right ports. ports "a" may be either the left or right port. port "b" is opposite from po rt "a". 5. if t ccs < maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs > maximum specified, then data from right port read is not valid until t ccs + t cd . t cwdd does not apply in this case. *= )=a'<< + ! ;" data in "a" clk "b" r/ w "b" addr "a" r/ w "a" clk "a" addr "b" no match match no match match valid t cwdd t cd t dc data out "b" 3490 drw 09 valid valid t ccs (5) t cd an an + 1 an + 2 an + 3 t cyc t ch t cl t sck t hck t sck r/ w address data out ce clken clk oe t s t h t cd t dc t cklz qn qn + 1 qn + 1 t ohz t olz t oe t ckhz 3490 drw 08 (1) (1) (1) (1)
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 9 *= ) +<<=-%

" /%" *= ) +<<=-% ;" b%" notes: 1. for t cyc = min.; data out coincident with the rising edge of the subsequent write clock can occur. to ensure writing to the correct add ress location, the write must be repeated on the second write clock rising edge. if ce = v il , invalid data will be written into array. the an+1 must be rewritten on the following cycle. 2. oe low throughout. 3. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 4. for t cyc > min.; oe may be used to avoid data out coincident with the rising edge of the subsequent write clock. use of oe will eliminate the need for the write to be repeated. r/ w address data in ce clken clk 3490 drw 11 an an + 1 t cyc t ch t h t cklz t cl t s dn + 1 qn t cd data out (3) oe t ohz (4) r/ w address data in ce clken clk 3490 drw 10 an an + 1 an + 1 an + 2 t cyc t ch t cl t h t cklz t cyc t ch t cl t s dn + 1 dn + 2 qn t cd t ckhz data out (3) (3) (1) (1) (1)
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 10 *'* 3cc>& 3* 3
" *'* 3c> +d=
" # the idt70914 provides a true synchronous dual-port static ram interface. registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal. an asynchronous output enable is provided to ease asynchronous bus interfacing. the internal write pulse width is dependent on the low to high transitions of the clock signal allowing the shortest possible realized cycle times. clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. a high on the ce input for one clock cycle will power down the internal circuitry to reduce static power consumption. notes: 1. 'h' = high voltage level steady state, 'h' = high voltage level one set-up time prior to the low-to-high clock transition, 'l ' = low voltage level steady state 'l' = low voltage level one set-up time prior to the low-to-high clock transition, 'x' = don't care, 'nc' = no change 2. clken = v il must be clocked in during power-up. 3. control signals are initialted and terminated on the rising edge of the clk, depending on their input level. when r/ w and ce are low, a write cycle is initiated on the low-to-high transition of the clk. termination of a write cycle is done on the next low-to-high transistion of the clk. 4. the register outputs are internal signals from the register inputs being clocked in or disabled by clken . mode inputs register inputs register outputs (4) clk (3) clken (2) addr datain addr dataout load "1" l hhhh load "0" lllll hold (do nothing) hxxncnc x h x x nc nc 3490 tbl 10 inputs outputs mode synchronous (3) asynchronous clk ce r/ w oe i/o 0-8 h x x high-z deselected, power-down ll x data in selected and write enabled lh l data out read selected and data output enable read x x h high-z outputs disabled 3490 tbl 09
6.42 idt70914s high-speed 36k (4k x 9) synchronous dual-port static ram military, industrial and commercial temperature ranges 11 (+c note: 1. industrial temperature range is available on selected tqfp packages in standard power. for specific speeds, packages and powers contact your sales office. idt xxxx a 999 a a device type power speed package process/ temperature range blank i (1) b commercial (0c to +70c) industrial (-40c to +85c) military (-55c to +85c) compliant to mil-prf-38535 qml j pf 68-pin plcc (j68-1) 80-pin tqfp (pn80-1) 12 15 20 25 commercial only commercial only commercial & military military only s standard power 70914 36k (4k x 9-bit) synchronous dual-port ram 3490 drw 12 ? ? ? speed in nanosecond s the idt logo is a registered trademark of integrated device technology, inc. '8- 3/10/99: initiated datasheet document history converted to new format cosmetic and typographical corrections page 2 and 3 added additional notes to pin configurations 6/7/99: changed drawing format 11/10/99: replaced idt logo 5/24/00: page 4 increased storage temperature parameter clarified t a parameter page 5 dc electrical parameters ? changed wording from "open" to "disabled" changed 200mv to 0mv in notes 1/12/01: removed pga pinout (obsolete package) changed cycle time of 12ns part from 17ns (58mhz) to 16ns (60mhz) corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com

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